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A method for timing closure in supply voltage scaled CMOS digital circuits with Dual-Vth devices / by Anne Lorraine S. Luna.

By: Luna, Anne Lorraine S.
Publisher: 2013Description: xiv, 88 leaves ; 28 cm.Subject(s): Digital integrated circuits | Metal -- Oxide semiconductorsDDC classification: 621.3815 Dissertation note: Thesis (Master of Science in Electrical Engineering) -- Masteral University of the Philippines, Diliman, Quezon City, 2013.
List(s) this item appears in: 2016 PNB

Thesis (Master of Science in Electrical Engineering) -- Masteral University of the Philippines, Diliman, Quezon City, 2013.

Bibliography: leaves 73-75.