A method for timing closure in supply voltage scaled CMOS digital circuits with Dual-Vth devices / (Record no. 376)

082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3815
Edition number 23
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Luna, Anne Lorraine S.
245 12 - TITLE STATEMENT
Title A method for timing closure in supply voltage scaled CMOS digital circuits with Dual-Vth devices /
Statement of responsibility, etc. by Anne Lorraine S. Luna.
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Date of publication, distribution, etc. 2013.
300 ## - PHYSICAL DESCRIPTION
Extent xiv, 88 leaves ;
Dimensions 28 cm
502 ## - DISSERTATION NOTE
Dissertation note Thesis (Master of Science in Electrical Engineering) --
Degree type Masteral
Name of granting institution University of the Philippines, Diliman, Quezon City, 2013.
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc. note Bibliography: leaves 73-75.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Digital integrated circuits.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Metal
General subdivision Oxide semiconductors.
993 ## - Local Record DB Identifier
DB Identifier PNB
YEAR 2016