Luna, Anne Lorraine S.
A method for timing closure in supply voltage scaled CMOS digital circuits with Dual-Vth devices / by Anne Lorraine S. Luna. - 2013. - xiv, 88 leaves ; 28 cm
Thesis (Master of Science in Electrical Engineering) --
Bibliography: leaves 73-75.
Digital integrated circuits.
Metal--Oxide semiconductors.
621.3815
A method for timing closure in supply voltage scaled CMOS digital circuits with Dual-Vth devices / by Anne Lorraine S. Luna. - 2013. - xiv, 88 leaves ; 28 cm
Thesis (Master of Science in Electrical Engineering) --
Bibliography: leaves 73-75.
Digital integrated circuits.
Metal--Oxide semiconductors.
621.3815